What is NVMe?
- “NVMe was designed from the ground up to provide a very high performance, low latency interface for PCIe SSD devices.
- “The interface was also designed to be highly parallel and highly scalable. The scalability, parallelism and inherent efficiency of NVMe allow the interface to scale up and down in performance without losing any of the benefits. These features allow the interface to be highly adaptable to a wide variety of system configurations and designs from laptops to very high end, highly parallel servers.”
NVMe Controller registers usage:
- Advertise capabilities of the controller
- Enable/disable/reset controller
- Setup addresses for admin queues
- Doorbell registers
NVMe Terminology:
- Submission Queue: a circular buffer with fixed slot size that the host use to submit commands for execution by the controller.
- Completion Queue: a circular buffer with fixed slot size used to post status of the completed commands.
- Door bell register: “Ring the bell” and notifies the SSD that the data is ready and waiting – used instead of polling of a register, better for power management.
- Port: is a queue set(a submission queue and completion quest is one queue set).
NVMe Queue operation:
- NVMe uses submission queues and completion queues for the management of memory for data transfer.
- Admin queues are for Admin commands; IO queues are for data transfer.
- Queues are managed in the host and device driver is responsible for talking b/w the host and controller.
- Addresses for Admin queues are programmed to controller registers( ie, Admin Submission Queue Base register/Admin Completion Queue Base register). For example, Send MemWr32 TLP with Address field Base+28h to program Admin Submission Queue Addresss.
NVMe Overview:
Queuing Interface:
Reference:
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